A Hardware-Aware AI Execution Framework for Edge AI Accelerators

Objective

Edge AI is poised to transform industries like healthcare, automation, and consumer electronics, but the rapid evolution of AI models clashes with the slow, rigid development of hardware accelerators. Custom accelerators, while efficient, take over a year to design, making them obsolete by the time they are deployed. Existing solutions also suffer from manual compiler customization and inefficient workload mappings, leading to wasted energy and increased latency. Building on the tools and methodologies developed in the ERC BINGO project, AigenTech tackles this challenge with an automated framework for exploring and generating AI accelerators, and automatically mapping and compiling AI workloads onto them, enabling rapid adaptation to new workloads. By integrating design space exploration, hardware generation, deep layer fusion mapping, and MLIR-based compilation, AigenTech reduces hardware design cycles from months to weeks and maximizes execution efficiency. This PoC will validate the framework through FPGA prototyping and industry benchmarking, create a web-based exploration platform prototype and engage our established and new semiconductor partners to pave the way for commercialization. As such, AigenTech will enable them to rapidly support future AI developments at high hardware efficiency, while reducing time-to-market.